1. Field
Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Description of the Related Art
NAND type flash memories are known as electrically rewritable and highly integrable nonvolatile semiconductor memory devices. Memory transistors of conventional NAND type flash memories have a stacked-gate structure in which a charge accumulation layer (floating gate) and a control gate are stacked via an insulation film. A NAND cell unit is configured by a plurality of memory transistors connected in series in a column direction with adjoining ones sharing their source or drain, and select gate transistors provided at the ends of the column of memory transistors. One end of the NAND cell unit is connected to a bit line, and the other end thereof is connected to a source line. A memory cell array is configured by NAND cell units being arranged in a matrix. NAND cell units arranged in a row direction are referred to as a NAND cell block. The gates of select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of memory transistors arranged in the same row constitute a word line. When N memory transistors are connected in series in a NAND cell unit, the number of word lines included in one NAND cell block is N.
In the aforementioned NAND type flash memories, miniaturization of the NAND type flash memories has reduced the gate length and the interval between adjoining transistors, which has brought about various problems described below. For example, these problems are (a) reduction in drain current controllability based on an electric field of the control gate due to increase in parasitic capacitance between adjoining gates, etc., short channel effect (SCE), and so on, (b) increase in an interference effect between adjoining gates, (c) increase in a leak current between adjoining electrodes, (d) leaning or collapsing of patterns during fabrication of the gates because of an increasing aspect ratio of the gate electrodes, (e) deterioration of data retention characteristics due to a significant reduction in the number of electrons that can be accumulated in the charge accumulation layer (the number of electrons per bit), and so on. Hence, conventional NAND type flash memories have almost reached the physical limit of miniaturization, with a significantly narrowed writing/erasing window of the memory cells.
“Three-dimensionally stacked” memories, in which memory cell transistors are stacked sterically to form many layers, are considered to be the main method for future integration. Specifically, a structure in which nitride film trap type (SONGS, MONOS) cells are stacked is proposed in many papers, and so on. The nitride film trap type cell structure has a merit in that it can be manufactured (stacked) easily, but its major problem is that its erasing characteristic and data retention characteristic are poorer than those of the floating gate type cell because of its nature of trapping electrons in the nitride film.
On the other hand, the conventional floating gate type memory cell structure for accumulating charges in the floating gate electrode is difficult to manufacture and stack, because it has an EB (Etch Back) structure in which a control gate electrode and an IPD film (Inter-Poly-Dielectric film or inter-gate insulating film) are provided not only over the upper surface of the floating gate electrode but also over the side surfaces thereof for securing a drive power (coupling ratio) of the control gate electrode. Further, according to one method for increasing the coupling ratio in order to widen the writing/erasing window of the memory cells, it is necessary to increase the thickness of the floating gate electrode. However, if the thickness of the floating gate electrode is increased in the EB structure in which the IPD film and the control gate electrode are stacked above the floating gate electrode, the word line is consequently raised upward and the aspect ratio is increased, exposing the problem (d) described above. Therefore, it is not easy to improve the coupling ratio.
Hence, as a cell structure for securing coupling ratio without extreme difficulty of manufacture, other than the stacked gate structure, the following structure has already been proposed. That is, in this structure, each control gate electrode is embedded between floating gates via an inter-gate insulating film such that the control gate electrode extends along the word line direction. This structure secures the coupling ratio by raising the potential of a write target cell through the control gate electrodes on both sides of the target cell.
However, as for these memory cells, simply stacking them means a simple increase in the number of manufacturing steps, and it is hence difficult to reduce the bit cost while ensuring an increase in the cell capacity that is balanced with the cost increase. Simple stacking is effective only by a bit cost shrink ratio=1/the number of stacked layers, i.e., the division by the number of layers, which means that the shrink ratio is small when the number of layers is large, leading to a high bit cost. Therefore, in the cell structure seeking a shrink by stacking, an object from a practical standpoint is to restrict the number of steps and the cost.